Mixture of negative bias temperature instability and hot-carrier driven threshold voltage degradation of 130 nm technology p-channel transistors

We present measurement results in form of threshold voltage drift plots, recovery traces and continuous capture emission time maps (CET maps) including Negative Bias Temperature Instability (NBTI) and HotCarrier driven Degradation (HCD). The measurements were performed on a 130 nm MOS transistor technology which is used for automotive and analog applications and has a nominal voltage of 1:5 V. Devices of l 1⁄4 100 nm, w 1⁄4 10 lm have been stressed using a 2-dimensional parameter space of gate and drain voltage combinations at elevated temperature (125 C). The chosen stress conditions include the homogeneous ðVds 1⁄4 0Þ and inhomogeneous ðVds VnomÞ NBTI case, the pure HCD ðVgs < VnomÞ case as well as the mixture of NBTI and HCD. The results clearly show that for increasing Vds > Vnom NBTI recovery becomes less severe and mainly the permanent degradation due to HCD endures after the end of stress. Furthermore there is a drift minimum of NBTI observable for a specific Vds. Using CET maps it is quite evident that for high stress times the probability density of emission becomes very small whereas for shorter stress times there is a recoverable component notable. 2014 Elsevier Ltd. All rights reserved.